quad-channel, hd image signal processor with precision timing core data sheet addi7004 rev. spd document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2008C2013 analog devices, inc. all rights reserved. technical support www.analog.com features support for ccd and cmos image sensors 4 afe channels 1.8 v analog and digital core supply voltage serial data output with reduced range lvds outputs differential analog inputs cds or sha configuration (cds bypass) with ?3 db, 0 db, +3 db, and +6 db gain 6 db to 42 db, 10-bit variable gain amplifier (vga) 14-bit, 72 mhz analog-to-digital converter (adc) black level clamp with variable level control precision timing core with 220 ps resolution @ 72 mhz applications digital video cameras digital still cameras medical imaging high speed industrial cameras general description the addi7004 is a highly integrated, quad-channel, hd image signal processor for high speed imaging applications. each channel is specified at pixel rates of up to 72 mhz and consists of a complete analog front end (afe) with adc conversion. the precision timing ? core allows adjustment of the correlated double sampler (cds) and sample-and-hold amplifier (sha) clocks with 220 ps resolution at 72 mhz operation. the addi7004 also contains a reduced range low voltage differential signaling (lvds) inter- face for the dual-channel data outputs. each analog front end includes black level clamping, a cds/sha, a vga, and a 72 mhz, 14-bit analog-to-digital converter (adc). operation is programmed using a 3-wire serial interface. packaged in a space-saving, 6 mm 6 mm, 76-ball bga, the addi7004 is specified over an operating temperature range of ?40c to +85c. functional block diagram dout0p dout0n dout1p dout1n dout2p dout2n dout3p dout3n tclk0p tclk0n tclk1p tclk1n dout4p dout4n dout5p dout5n dout6p dout6n dout7p dout7n inp_b inm_b inp_c inm_c inp_d shp shd clpob pblk dcr inm_d afe2 afe3 afe4 inp_a inm_a ?3db, 0db, +3db, +6db cds/ sha vga 6db ~ 42db clamp vref adc afe1 reduced range lvds interface vd hd sdata sck cli rstb sl precision timing core sync generator internal clocks internal registers addi7004 notes 1. the circuitry for afe1 to afe4 is identical. 07799-001 figure 1. for more information on the addi7004, email analog devices, inc., at afe.ccd@analog.com.
addi7004 data sheet rev. spd | page 2 of 2 notes ?2008C2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07799f-0-4/13(spd)
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